In various types of memory devices, one or more bit lines are used to access memory bit cells. In some memory configurations, during a read operation, a bit line coupled to a bit cell is used to obtain the logic value of a data bit stored at the bit cell. A bit line is precharged to a predetermined voltage (e.g., corresponding to a logical high value), and a word line is asserted. The bit line settles to a value indicative of a data bit stored at the bit cell. In some instances, the bit line is pulled down towards a logical low voltage value (e.g., logical ‘0’) at a relatively slow rate. A weak (relatively slow) transition of the bit line from ‘1’ to ‘0’ is sometimes referred to as a “weak bit” issue and results from process variation. When considering the 6σ (six standard deviations from mean) time for the bit line to settle at ‘0’ during a read operation, a variation in settling time greater than 50% has been observed. The weak bit issue negatively impacts memory access time and performance of various circuit applications.